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12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition.

, , , and . CICC, page 1-4. IEEE, (2017)

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x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression., , , , , and . VLSIC, page 134-135. IEEE, (2012)Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers., , and . VLSI Circuits, page 1-2. IEEE, (2016)Robust VLSI circuit design & systems for sustainable society., , , , and . ISSCC, page 500-501. IEEE, (2012)7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage., , , , , and . ISSCC, page 1-3. IEEE, (2015)0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives., , and . ISQED, page 81-86. IEEE, (2017)Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network., , , , and . ISCAS, page 1-5. IEEE, (2018)Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAM., , , and . ESSDERC, page 46-49. IEEE, (2018)Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature., , and . NVMTS, page 1-5. IEEE, (2018)Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM., , , and . CICC, page 1-4. IEEE, (2011)Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data., and . A-SSCC, page 161-164. IEEE, (2017)