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Fundamental CAD algorithms.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (12): 1449-1475 (2000)

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Some theoretical aspects of algorithmic routing., and . DAC, page 23-31. ACM, (1977)A Note on Three-Valued Logic Simulation.. IEEE Trans. Computers, 21 (4): 399-402 (1972)Functional Partitioning and Simulation of Digital Circuits.. IEEE Trans. Computers, 19 (11): 1038-1046 (1970)Procedures for Eliminating Static and Dynamic Hazards in Test Generation., and . IEEE Trans. Computers, 23 (10): 1069-1078 (1974)On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays., and . IEEE Trans. Computers, 33 (1): 21-27 (1984)Test Schedules for VLSI Circuits Having Built-In Test Hardware., and . IEEE Trans. Computers, 35 (4): 361-367 (1986)Roving Emulation as a Fault Detection Mechanism., and . IEEE Trans. Computers, 35 (11): 933-939 (1986)A Test and Maintenance Controller for a Module Containing Testable Chips., and . ITC, page 502-513. IEEE Computer Society, (1988)Generation of optimal code for expressions via factorization.. Commun. ACM, 12 (6): 333-340 (1969)BALLAST: a methodology for partial scan design., , and . FTCS, page 118-125. IEEE Computer Society, (1989)