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Disambiguation of "Roy, Subhendu"

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A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders.

, , , and . ISLPED, page 1-6. IEEE, (2017)

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Roy Hornig

Beschreibung mikro-rheologischer Vorgänge und resultierender Verbundstrukturen beim Elastomermischprozeß im Innenmischer durch rheologische Untersuchungen. NA Halle-Wittenberg, (2009)

Trina Roy

David Roy

Smritindu Roy

Wolfgang Roy

 

Other publications of authors with the same name

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (10): 1517-1530 (2014)Large Scale VLSI Circuit Simulation Using Point Relaxation., , , and . CSC, page 343-347. CSREA Press, (2010)Clock tree resynthesis for multi-corner multi-mode timing closure., , , and . ISPD, page 69-76. ACM, (2014)Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs., , , and . ASP-DAC, page 249-254. IEEE, (2015)Design for manufacturability and reliability in extreme-scaling VLSI., , , , , and . Sci. China Inf. Sci., 59 (6): 061406:1-061406:23 (2016)Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session)., , , and . CoRR, (2014)LRR-DPUF: learning resilient and reliable digital physical unclonable function., , , and . ICCAD, page 46. ACM, (2016)SD-PUF: Spliced Digital Physical Unclonable Function., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (5): 927-940 (2018)Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (5): 820-831 (2016)OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions., , , and . DAC, page 129:1-129:6. ACM, (2015)