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A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test., , , , and . ICCAD, page 240-245. IEEE Computer Society, (2007)Diagnosing multiple transition faults in the absence of timing information., , , and . ACM Great Lakes Symposium on VLSI, page 193-196. ACM, (2005)Automated debugging with high level abstraction and refinement., and . HLDVT, page 26-31. IEEE Computer Society, (2009)Toward Automated ECOs in FPGAs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (1): 18-30 (2011)Improved Design Debugging Using Maximum Satisfiability., , , , and . FMCAD, page 13-19. IEEE Computer Society, (2007)An Automated Framework for Correction and Debug of PSL Assertions., , and . MTV, page 9-12. IEEE Computer Society, (2010)Abstraction and Refinement Techniques in Automated Design Debugging., and . MTV, page 88-93. IEEE Computer Society, (2006)Managing verification error traces with bounded model debugging., , and . ASP-DAC, page 601-606. IEEE, (2010)The day Sherlock Holmes decided to do EDA., and . DAC, page 631-634. ACM, (2009)Towards automated ECOs in FPGAs., , , and . FPGA, page 3-12. ACM, (2009)