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An efficient approach for design and testing of FPGA programming using Lab VIEW.

B. Reddy, N. Suresh, J. Ramesh, T. Pavithra, Y. Bahulya, P. Edavoor, and S. Ram. ICACCI, page 543-548. IEEE, (2015)

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Heinrich J J Mieschendahl

J J M Ramakers

Norbert J J Bock

Ulrich J J Longerich

Other publications of authors with the same name

Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval.A. Samantaray, P. Edavoor, and A. Rahulkar. IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 104-113 (2023)A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis.A. Samantaray, P. Edavoor, and A. Rahulkar. IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3949-3953 (2022)Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA.P. Das, P. Edavoor, S. Raveendran, S. Rathore, and A. Rahulkar. ISED, page 1-6. IEEE, (2017)A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction.A. Samantaray, A. Rahulkar, and P. Edavoor. Circuits Syst. Signal Process., 40 (11): 5401-5420 (2021)FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images.P. Edavoor, S. Raveendran, A. V., S. P., K. Nithin, and M. Vasantha. ICCCNT, page 35:1-35:6. ACM, (2016)Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter.S. Raveendran, P. Edavoor, N. Kumar, and M. Vasantha. TENCON, page 1813-1817. IEEE, (2018)A New Approach to the Design and Implementation of a Family of Multiplier Free Orthogonal Wavelet Filter Banks.A. Samantaray, P. Edavoor, and A. Rahulkar. IEEE Trans. Circuits Syst. Video Technol., 32 (4): 1942-1954 (2022)Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications.P. Edavoor, S. Raveendran, and A. Rahulkar. J. Circuits Syst. Comput., 30 (8): 2150138:1-2150138:27 (2021)Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.P. Edavoor, A. Raveendran, D. Selvakumar, V. Desalphine, S. Dharani, and G. Raut. VLSID, page 252-257. IEEE, (2023)Reversible Logic Implementation of Image Denoising for Grayscale Images.S. Raveendran, P. Edavoor, N. B., and M. Vasantha. MWSCAS, page 138-141. IEEE, (2020)

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Disambiguation of "Edavoor, Pranose J."

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An efficient approach for design and testing of FPGA programming using Lab VIEW.

Please choose a person to relate this publication to

Heinrich J J Mieschendahl

J J M Ramakers

Norbert J J Bock

Ulrich J J Longerich

Ulrich J J Longerich

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Edavoor, Pranose J."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An efficient approach for design and testing of FPGA programming using Lab VIEW.

Please choose a person to relate this publication to

Heinrich J J Mieschendahl

J J M Ramakers

Norbert J J Bock

Ulrich J J Longerich

Ulrich J J Longerich

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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An efficient approach for design and testing of FPGA programming using Lab VIEW.