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Disambiguation of "Hashimoto, Masanori"

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Critical path isolation for time-to-failure extension and lower voltage operation.

, , and . ICCAD, page 63. ACM, (2016)

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Setsuko Hashimoto

Marcelo Hashimoto

Jujiro Hashimoto

Yoko Hashimoto

 

Other publications of authors with the same name

A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design., , and . DAC, page 446-451. ACM Press, (1999)Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 724-731 (2007)Transistor Sizing of LCD Driver Circuit for Technology Migration., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2712-2717 (2007)Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2441-2446 (2010)Successive Pad Assignment for Minimizing Supply Voltage Drop., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3429-3436 (2005)On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3491-3499 (2006)A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2292-2300 (2012)Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices., , , , , and . IEICE Trans. Inf. Syst., 96-D (8): 1624-1631 (2013)Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate., and . IEICE Trans. Electron., 102-C (4): 296-302 (2019)A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (12): 1447-1455 (2020)