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A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.

I. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, and H. Smith. DATE, page 144-149. IEEE Computer Society, (2004)

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Alireza Alinaghi

Alina Boberg

Alina Balandin

Alina Chanaewa

Alina Streblyanska

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Electrical-thermal co-analysis for power delivery networks in 3D system integration.J. Xie, D. Chung, M. Swaminathan, M. McAllister, A. Deutsch, L. Jiang, and B. Rubin. 3DIC, page 1-4. IEEE, (2009)Single-chip 4×500-MBd CMOS transceiver.A. Widmer, K. Wrenner, H. Ainspan, B. Parker, P. Austruy, B. Brezzo, A. Haen, J. Ewen, M. Soyuer, A. Blanc and 3 other author(s). IEEE J. Solid State Circuits, 31 (12): 2004-2014 (1996)Electrical characteristics of interconnections for high-performance systems.A. Deutsch. Proc. IEEE, 86 (2): 315-357 (1998)Prediction and Comparison of High-Performance On-Chip Global Interconnection.Y. Zhang, X. Hu, A. Deutsch, A. Engin, J. Buckwalter, and C. Cheng. IEEE Trans. Very Large Scale Integr. Syst., 19 (7): 1154-1166 (2011)Low power passive equalizer optimization using tritonic step response.L. Zhang, W. Yu, H. Zhu, A. Deutsch, G. Katopis, D. Dreps, E. Kuh, and C. Cheng. DAC, page 570-573. ACM, (2008)High-Speed Signal Propagation on Lossy Transmission Lines.A. Deutsch, G. Kopcsay, V. Ranieri, J. Cataldo, E. Galligan, W. Graham, R. McGouey, S. Nunes, J. Paraszczak, J. Ritsko and 3 other author(s). IBM J. Res. Dev., 34 (4): 601-615 (1990)Performance limits of electrical cables for intrasystem communication.A. Deutsch, G. Arjavalingam, C. Surovic, A. Lanzetta, K. Fogel, F. Dowany, and M. Ritter. IBM J. Res. Dev., 38 (6): 659-672 (1994)Electrical characterization and performance limits of a flexible cable.A. Deutsch, D. Dranchak, G. Arjavalingam, C. Surovic, J. Tam, G. Kopcsay, and J. Gillett. IBM J. Res. Dev., 37 (1): 22-38 (1993)A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis.G. Kopcsay, B. Krauter, D. Widiger, A. Deutsch, B. Rubin, and H. Smith. IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 695-711 (2002)On-chip wiring design challenges for gigahertz operation.A. Deutsch, P. Coteus, G. Kopcsay, H. Smith, C. Surovic, B. Krauter, D. Edelstein, and P. Restle. Proc. IEEE, 89 (4): 529-555 (2001)

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Disambiguation of "Deutsch, Alina"

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A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.

Please choose a person to relate this publication to

Alireza Alinaghi

Alina Boberg

Alina Balandin

Alina Chanaewa

Alina Streblyanska

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Deutsch, Alina"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.

Please choose a person to relate this publication to

Alireza Alinaghi

Alina Boberg

Alina Balandin

Alina Chanaewa

Alina Streblyanska

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.