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Disambiguation of "Kuijk, Maarten"

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Wafer-level package interconnect options.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (6): 654-659 (2006)

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Maarten Boersma

Maarten Schroen

Maarten Löffler

Maarten Bynens

Maarten Thomas

 

Other publications of authors with the same name

An 8-Gb/s capacitively coupled receiver with high common-mode rejection for uncoded data., and . IEEE J. Solid State Circuits, 39 (11): 1909-1915 (2004)Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate., , , , , , and . IEEE J. Solid State Circuits, 41 (9): 2040-2051 (2006)A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS., , , , , and . IEEE J. Solid State Circuits, 44 (7): 1942-1949 (2009)A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS., , , , and . ISSCC, page 296-297. IEEE, (2010)A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS., , , , and . ESSCIRC, page 410-413. IEEE, (2008)A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS., , , , , , and . IEEE J. Solid State Circuits, 43 (12): 2693-2705 (2008)Efficient Link Architecture for On-Chip Serial links and Networks., , , , , , and . SoC, page 1-4. IEEE, (2006)21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS., , , , , and . ISSCC, page 366-367. IEEE, (2014)A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS., , , , and . IEEE J. Solid State Circuits, 45 (10): 2080-2090 (2010)A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS., , , , and . IEEE J. Solid State Circuits, 44 (3): 874-882 (2009)