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A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration.

, , and . A-SSCC, page 353-356. IEEE, (2014)

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A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1005-1014 (2015)A 0.1~4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2012)An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65 nm CMOS., , , and . Microelectron. J., 46 (1): 81-95 (2015)An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (11): 3113-3124 (2017)A Flexible Continuous-Time Δ Σ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 872-880 (2017)MMCNN: A Multi-branch Multi-scale Convolutional Neural Network for Motor Imagery Classification., , , , , and . ECML/PKDD (3), volume 12459 of Lecture Notes in Computer Science, page 736-751. Springer, (2020)-80dBm∼0dBm dynamic range, 30mV/dB detection sensitivity piecewise RSSI for SDR/CR receivers., , , and . MWSCAS, page 89-92. IEEE, (2014)A 0.5-30GHz wideband differential CMOS T/R switch with independent bias and leakage cancellation techniques., , , and . ISCAS, page 449-452. IEEE, (2015)A 0.1-1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration., , and . A-SSCC, page 353-356. IEEE, (2014)A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 944-957 (2015)