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Efficient encoding for dual-diagonal structured LDPC codes based on parity bit prediction and correction., , and . APCCAS, page 1648-1651. IEEE, (2008)A High Throughput H-QC LDPC Decoder., and . ISCAS, page 1649-1652. IEEE, (2007)Reconfigurable Platform for Content Science Research., , , , , , and . RTCSA, page 481-486. IEEE Computer Society, (2005)Node Operation Reduced Decoding for LDPC Codes., and . ISCAS, page 896-899. IEEE, (2009)Support vector machine FPGA implementation for video shot boundary detection application., , and . SoCC, page 239-242. IEEE, (2009)3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design., , , , , , and . ICME, page 9. IEEE Computer Society, (2007)Switching activity reducing layered decoding algorithm for LDPC codes., , and . ISCAS, page 528-531. IEEE, (2008)Operation reduced low-density parity-check decoding algorithms for low power communication systems., , and . Int. J. Commun. Syst., 26 (1): 68-83 (2013)Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism., , and . VTC Spring, page 1423-1427. IEEE, (2008)Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (2): 773-780 (2011)