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A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications., , , , , , , , , and 2 other author(s). ISSCC, page 154-155. IEEE, (2009)Efficient Spatial-Temporal Error Concealment Algorithm and Hardware Architecture Design for H.264/AVC., , , and . IEEE Trans. Circuits Syst. Video Techn., 20 (11): 1409-1422 (2010)Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements., , and . IEEE Trans. Circuits Syst. Video Techn., 15 (9): 1156-1169 (2005)A hardware accelerator for video segmentation using programmable morphology PE array., , and . ISCAS (4), page 341-344. IEEE, (2002)Enhanced temporal error concealment algorithm with edge-sensitive processing order., , , and . ISCAS, page 3466-3469. IEEE, (2008)Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach., , , , and . VCIP, volume 5150 of Proceedings of SPIE, page 1521-1530. SPIE, (2003)Distributed video codec with spatiotemporal side information., , , , and . ISCAS, page 1-4. IEEE, (2017)Occlusion-aware Video Temporal Consistency., , and . ACM Multimedia, page 777-785. ACM, (2017)Perceptual Quality-Regulable Video Coding System With Region-Based Rate Control Scheme., , , and . IEEE Trans. Image Processing, 22 (6): 2247-2258 (2013)A Novel Gaming Video Encoding Process Using In-Game Motion Vectors., , and . IEEE Trans. Circuits Syst. Video Techn., 30 (7): 2207-2214 (2020)