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A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm., and . IEEE Trans. Circuits Syst. Video Techn., 8 (2): 124-127 (1998)Reconfigurable architecture for video applications., , , , and . SoCC, page 21-24. IEEE, (2007)Error concealment of lost motion vectors with overlapped motion compensation., , and . IEEE Trans. Circuits Syst. Video Techn., 7 (3): 560-563 (1997)Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000., , , and . IEEE Trans. Circuits Syst. Video Techn., 13 (3): 219-230 (2003)Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors., , , and . IEEE Trans. Circuits Syst. Video Techn., 13 (1): 111-117 (2003)An efficient architecture for two-dimensional discrete wavelet transform., and . IEEE Trans. Circuits Syst. Video Techn., 11 (4): 536-545 (2001)A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications., , , , , , , , , and 2 other author(s). ISSCC, page 154-155. IEEE, (2009)Low-power multi-processor system architecture design for universal biomedical signal processing., , and . ISCAS, page 857-860. IEEE, (2013)CDSP: an application-specific digital signal processor for third generation wireless communications., , and . IEEE Trans. Consumer Electronics, 47 (3): 672-677 (2001)Fast belief propagation process element for high-quality stereo estimation., , , , and . ICASSP, page 745-748. IEEE, (2009)