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Disambiguation of "Kasahara, Hironori"

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A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.

, , , , , , , , , , , , , and . ISSCC, page 100-590. IEEE, (2007)

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Hironori Kumeno

Hironori Tokuno

 

Other publications of authors with the same name

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (4): 902-910 (2008)What Will 2022 Look Like? The IEEE CS 2022 Report., , , , , , , , and . Computer, 48 (3): 68-76 (2015)A Compilation Scheme for Macro-Dataflow Computation on Hierarchical Multiprocessor Systems., , , and . ICPP (2), page 294-295. Pennsylvania State University Press, (1990)0-271-00728-1.Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP., , , , and . Int. J. Parallel Program., 31 (3): 211-223 (2003)Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications., , , , , and . Int. J. Parallel Program., 47 (3): 343-344 (2019)Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler., , , , , , , and . IEICE Trans. Electron., 103-C (3): 98-109 (2020)Parallel processing of robot arm dynamic control computation on multimicroprocessors.. Microprocess. Microsystems, 14 (1): 3-9 (1990)A Data-Localization Compilation Scheme Using Partial-Static Task Assignment for Fortran Coarse-Grain Parallel Processing., and . Parallel Comput., 24 (3-4): 579-596 (1998)Message from the CAP 2017 Organizing Committee., , and . COMPSAC (1), page 458. IEEE Computer Society, (2017)Parallel processing scheme of a basic block in a fortran program on oscar., , , and . Syst. Comput. Jpn., 22 (11): 1-13 (1991)