( en | de | ru )

 

Disambiguation of "Hanyu, Takahiro"

Author of the publication

copydeleteadd this publication to your clipboard
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.

, , and . ISMVL, page 70-75. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Takahiro Kato

Hanyu Ye

Takahiro Moriyama

Takahiro Kirihara

Takahiro Nishiyama

 

Other publications of authors with the same name

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing., , , , and . CoRR, (2015)High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure., , , , and . ISCAS, page 1-5. IEEE, (2018)Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only)., and . FPGA, page 291. ACM, (2018)Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link., , , and . APCCAS, page 683-686. IEEE, (2014)Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system., , , and . ISCAS, page 2067-2070. IEEE, (2011)Efficient CMOS Invertible Logic Using Stochastic Computing., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (6): 2263-2274 (2019)NoC-MRAM architecture for memory-based computing: Database-search case study., , , , , , , and . NEWCAS, page 309-312. IEEE, (2017)A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception., , , , , and . J. Signal Process. Syst., 90 (5): 709-725 (2018)Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing., and . IEICE Trans. Electron., 89-C (11): 1598-1604 (2006)Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device., and . IEICE Trans. Electron., 94-C (8): 1302-1310 (2011)