( en | de | ru )

 

Disambiguation of "Ito, Junichi"

Author of the publication

copydeleteadd this publication to your clipboard
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

, , , , , , , , , , , , and . ISSCC, page 132-133. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nobutaka Ito

Junichi Nonaka

Akio Ito

Takao Ito

Hisao Ito

 

Other publications of authors with the same name

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)A Genetic Algorithm to Improve Agent-Oriented Natural Language Interpreters., , and . GECCO (2), volume 3103 of Lecture Notes in Computer Science, page 1307-1309. Springer, (2004)Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU., , , , , and . VLSIC, page 1-2. IEEE, (2014)Active and Precise Control of Microdroplet Division Using Horizontal Pneumatic Valves in Bifurcating Microchannel., , , and . Micromachines, 4 (2): 197-205 (2013)Economic and institutional reform packages and their impact on productivity: A case study of Chinese township and village enterprises. Journal of Comparative Economics, 34 (1): 167--190 (March 2006)A GIS-based Model for the Assessment of Energy and Environmental Contributions of Distributed Energy Systems., , , and . EnviroInfo, page 107-114. Shaker Verlag, Aachen, (2006)7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)