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Disambiguation of "Sun, Hyuk"

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A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers.

, , , , , and . A-SSCC, page 325-328. IEEE, (2016)

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Young-Hyuk Joo

Hyuk-Cheol Kwon

Yü-Sün Sun

Woo-Hyuk Byun

Min-Hyuk Kim

 

Other publications of authors with the same name

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers., , , , , and . A-SSCC, page 325-328. IEEE, (2016)A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier., , , , and . CICC, page 1-4. IEEE, (2017)An Oversampling Stochastic ADC Using VCO-Based Quantizers., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4037-4050 (2018)Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency., , and . MWSCAS, page 1-4. IEEE, (2015)MDLL/PLL dual-path clock generator., and . MWSCAS, page 1-4. IEEE, (2015)A VCO-based spatial averaging stochastic ADC., , and . ICECS, page 272-275. IEEE, (2015)A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL., , , , and . CICC, page 1-4. IEEE, (2017)A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator., , , , and . IEEE J. Solid State Circuits, 55 (2): 426-438 (2020)A 10-Bit 800-MHz 19-mW CMOS ADC., , and . IEEE J. Solid State Circuits, 49 (4): 935-949 (2014)A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization., , , , and . CICC, page 1-4. IEEE, (2017)