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Disambiguation of "Beakes, Michael P."

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A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.

, , , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1744-1755 (2016)

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Michael P Maier

Michael P Eichenlaub

Michael P Braun

Michael P Schodlok

P Günther

 

Other publications of authors with the same name

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (8): 2009-2017 (2013)An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 47 (4): 884-896 (2012)A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (12): 2633-2645 (2005)TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip., , , , , , , , , and 8 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1537-1557 (2015)A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 58 (4): 1074-1086 (2023)Errata Erratum to Ä 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . IEEE J. Solid State Circuits, 55 (4): 1124 (2020)A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1744-1755 (2016)A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 55 (1): 19-26 (2020)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 50 (12): 3120-3132 (2015)A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 41 (12): 2885-2900 (2006)