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Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach.

, , , , and . ISQED, page 573-578. IEEE Computer Society, (2005)

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Technologies and Utilization fo Field Programmable Gate Arrays., , and . FPL, volume 705 of Lecture Notes in Computer Science, page 11-25. Springer, (1992)An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies., and . ISCAS, page 265-268. IEEE, (1994)Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic., , and . ISCAS, IEEE, (2006)High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling., , , , and . VLSI Design, (2007)Hybrid Trust Model for Internet Routing, , and . CoRR, (2011)Design and Implementation of Viterbi Decoder with FPGAs., , and . VLSI Signal Processing, 21 (1): 5-14 (1999)DSP system integration and prototyping with FPGAS., , , and . VLSI Signal Processing, 6 (2): 155-172 (1993)Objectives for New Error Criteria for Mobile Broadcasting of Streaming Audiovisual Services., , , and . EURASIP J. Adv. Signal Process., (2008)Current Challenges in Embedded Communication Systems., , and . Int. J. Embed. Real Time Commun. Syst., 1 (1): 1-21 (2010)A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T., , , and . ISCAS (4), page 382-385. IEEE, (1999)