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Disambiguation of "Andreani, Pietro"

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A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier.

, , , and . ISCAS (1), page 346-349. IEEE, (1999)

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Brigitte Andréani

Stefano Pietro

Pietro Cortona

Pietro Moretto

Pietro Tierno

 

Other publications of authors with the same name

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing., , , and . ISCAS, page 169-172. IEEE, (2013)A study of phase noise in colpitts and LC-tank CMOS oscillators., , , and . IEEE J. Solid State Circuits, 40 (5): 1107-1118 (2005)A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise., , , , and . IEEE J. Solid State Circuits, 57 (9): 2802-2811 (2022)A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers., , , and . IEEE J. Solid State Circuits, 49 (3): 646-656 (2014)A 1-1 MASH 2-D vernier time-to-digital converter with 2nd-order noise shaping., and . ISCAS, page 1324-1327. IEEE, (2014)Digital background calibration in continuous-time delta-sigma analog to digital converters., , , , and . NORCAS, page 1-4. IEEE, (2015)A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs., , and . ESSCIRC, page 459-462. IEEE, (2011)A Class-D CMOS DCO with an on-chip LDO., , and . ESSCIRC, page 335-338. IEEE, (2014)Low-phase-noise 3.4-4.5 GHz dynamic-bias class-C CMOS VCOs with a FoM of 191 dBc/Hz., and . ESSCIRC, page 406-409. IEEE, (2012)A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO., , and . ISSCC, page 354-356. IEEE, (2012)