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Disambiguation of "Arsovski, Igor"

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A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements.

, , , , , , , , , , , and . ISSCC, page 254-256. IEEE, (2011)

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Igor Barabash

Das Bildzitat im Internet. Uni München, (2009)

Igor Smolitsch

Igor Popov

Igor Kasko

Igor Herrmann

 

Other publications of authors with the same name

Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines., and . CICC, page 447-450. IEEE, (2005)A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories., and . IEEE J. Solid State Circuits, 38 (11): 1958-1966 (2003)A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme., , and . IEEE J. Solid State Circuits, 38 (1): 155-158 (2003)1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing., , , and . VLSIC, page 116-117. IEEE, (2012)Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories., and . CICC, page 453-456. IEEE, (2006)A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements., , , , , , , , , and 2 other author(s). ISSCC, page 254-256. IEEE, (2011)1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%., , , , , , and . IEEE J. Solid State Circuits, 53 (1): 155-163 (2018)A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 97-106 (2012)A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction., , , , , , , , , and 1 other author(s). ISSCC, page 322-323. IEEE, (2013)A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation., , , and . IEEE J. Solid State Circuits, 48 (4): 932-939 (2013)