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Disambiguation of "Pamarti, Sudhakar"

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A Theoretical Analysis of Split Delta-Sigma ADCs.

. ISCAS, page 493-496. IEEE, (2007)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Sudhakar Motiram Chaudhari

Yamini Sudhakar Avadhut

 

Other publications of authors with the same name

Mitigating Timing Errors in Time-Interleaved ADCs: a signal conditioning approach, and . CoRR, (2012)A precisely-timed energy injection technique achieving 58/10/2μs start-up in 1.84/10/50MHz crystal oscillators., and . CICC, page 1-4. IEEE, (2017)A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation., , and . CICC, page 121-124. IEEE, (2009)A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability., , , , , , , , , and 3 other author(s). ISSCC, page 206-208. IEEE, (2012)A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology., , , and . IEEE J. Solid State Circuits, 52 (3): 781-798 (2017)Errata for "Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor"., and . IEEE J. Solid State Circuits, 53 (9): 2733 (2018)A Spur-Free MASH DDSM With High-Order Filtered Dither., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (9): 585-589 (2011)Clock/Frequency Generation Circuits and Systems., , , , and . J. Electr. Comput. Eng., (2012)A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS., , , , , , , and . ESSCIRC, page 435-438. IEEE, (2021)23.8 A 34V charge pump in 65nm bulk CMOS technology., , , and . ISSCC, page 408-409. IEEE, (2014)