( en | de | ru )

 

Disambiguation of "Bertozzi, Davide"

Author of the publication

copydeleteadd this publication to your clipboard
xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.

, , , , , and . DATE, page 1188-1193. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Davide Cadamuro

Davide Pennino

Davide Cantoni

Davide Batic

Davide Pagani

 

Other publications of authors with the same name

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip., , , and . ACM Great Lakes Symposium on VLSI, page 125-128. ACM, (2009)Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels., and . AISTECS@HiPEAC, page 12-17. ACM, (2017)SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs., , , and . Embedded Systems Design and Verification, CRC Press, (2009)Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip., , , and . Embedded Systems Design and Verification, CRC Press, (2009)An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing., and . DCIS, page 1-6. IEEE, (2019)Interdisciplinary design of a research experience on microelectronic systems for K-12 students., and . EWME, page 64-69. IEEE, (2014)Energy-Reliability trade-Off for NoCs., , and . Networks on Chip, Kluwer / Springer, (2003)Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology., , , , , , , , , and . Trans. High Perform. Embed. Archit. Compil., (2007)Power aware network interface management for streaming multimedia., , and . WCNC, page 926-930. IEEE, (2002)PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer., , , and . JETC, 12 (4): 44:1-44:28 (2016)