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A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time ΔΣ ADC in 28 nm CMOS with excess-loop-delay compensation embedded in SAR quantizer., , , , and . VLSIC, page 292-. IEEE, (2015)A single-chip universal cable set-top box/modem transceiver., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 34 (11): 1647-1660 (1999)A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit., , , , , , , , , and 25 other author(s). IEEE J. Solid State Circuits, 43 (5): 1101-1118 (2008)A stereo asynchronous digital sample-rate converter for digital audio., and . IEEE J. Solid State Circuits, 29 (4): 481-488 (April 1994)A Monolithic Asynchronous Sample-Rate Converter for Digital Audio., and . ISCAS, page 1963-1966. IEEE, (1993)A 70 dB MTPR Integrated Programmable Gain/Bandwidth Fourth-Order Chebyshev High-Pass Filter for ADSL/VDSL Receivers in 65 nm CMOS., , , and . IEEE J. Solid State Circuits, 44 (4): 1290-1297 (2009)A stereo multibit ΣΔ DAC with asynchronous master-clock interface., , and . IEEE J. Solid State Circuits, 31 (12): 1881-1887 (1996)A single-chip universal digital satellite receiver with 480-MHz IF input., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 34 (11): 1634-1646 (1999)A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS., , , , and . VLSIC, page 1-2. IEEE, (2014)An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)