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Disambiguation of "Craninckx, Jan"

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2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS.

, , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tsai-Yu Jansen

Einfluss der Konversion laparoskopischer Operationen auf Tumorwachstum, hepatische Metastasierung und Tumorangiogenese. Uni Heidelberg, (2010)

Dirk Jansen

Temperaturkorrektur von mit dem Falling-Weight-Deflectometer gemessenen Deflexionen auf Asphaltbefestigungen. Uni Duisburg-Essen, (2009)

Matthäus Janczyk

Synthese funktionalisierter Trinukleotide und ihre Anwendung bei der Randomisierung. Uni Greifswald, (2009)

Christoph Janello

Wertschöpfung im digitalisierten Buchmarkt. Uni München, (2010)

Richard Janissen

Biomolecular based nano-manipulation with a combined atomic force microscope and single molecule fluorescence setup. Uni Düsseldorf, (2009)
 

Other publications of authors with the same name

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers., , , , , , and . ISSCC, page 62-64. IEEE, (2011)A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS., , , , , and . ISSCC, page 374-376. IEEE, (2011)Clock synthesis design.. ISSCC, page 510. IEEE, (2009)An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power., , , , and . ESSCIRC, page 176-179. IEEE, (2015)A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter., , , and . IEEE J. Solid State Circuits, 50 (5): 1203-1213 (2015)New Associate Editor.. IEEE J. Solid State Circuits, 53 (5): 1243 (2018)A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers., , , , , , , and . IEEE J. Solid State Circuits, 46 (7): 1659-1671 (2011)Correction to Ä 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range"., , , , and . IEEE J. Solid State Circuits, 50 (2): 619 (2015)A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth., , , and . IEEE J. Solid State Circuits, 54 (12): 3503-3512 (2019)A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range., , , , and . IEEE J. Solid State Circuits, 49 (5): 1173-1183 (2014)