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Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (2): 298-302 (2009)Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits., and . IET Comput. Digit. Tech., 5 (4): 306-315 (2011)Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction., , and . ISQED, page 459-464. IEEE Computer Society, (2004)On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD., , , and . IOLTS, page 123-128. IEEE Computer Society, (2008)Concurrent Error Detection in Asynchronous Burst-Mode Controllers., and . DATE, page 1272-1277. IEEE Computer Society, (2005)Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit., , and . Asian Test Symposium, page 319-324. IEEE Computer Society, (2001)On Concurrent Error Detection with Bounded Latency in FSMs., , and . DATE, page 596-603. IEEE Computer Society, (2004)On Compaction-Based Concurrent Error Detection., , and . IOLTS, page 157. IEEE Computer Society, (2003)Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines., and . IEEE Trans. Computers, 56 (6): 785-798 (2007)Predictive analysis for projecting test compression levels., and . ITC, page 275-284. IEEE Computer Society, (2010)