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Disambiguation of "Vallero, Alessandro"

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RIIF-2: Toward the next generation reliability information interchange format.

, , , , , and . IOLTS, page 173-178. IEEE, (2016)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sara Vallero

Alessandro Valeri

Fluorescence resonance energy transfer between multiple chromophores studied by single-molecule spectroscopy. Uni Düsseldorf, (2009)

Alessandro Zivelonghi

Alessandro Nova

Alessandro Topa

 

Other publications of authors with the same name

Memristive Biosensors Integration With Microfluidic Platform., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (12): 2120-2127 (2016)Resistance impact by long connections on electrical behavior of integrated Memristive Biosensors., , , , and . ISCAS, page 385-388. IEEE, (2016)ReDO: Cross-Layer Multi-Objective Design-Exploration Framework for Efficient Soft Error Resilient Systems., , and . IEEE Trans. Computers, 67 (10): 1462-1477 (2018)A novel methodology to increase fault tolerance in autonomous FPGA-based systems., , , , , and . IOLTS, page 87-92. IEEE, (2014)Bayesian models for early cross-layer reliability analysis and design space exploration., , , and . IOLTS, page 143-146. IEEE, (2019)Bayesian network early reliability evaluation analysis for both permanent and transient faults., , , , , , , and . IOLTS, page 7-12. IEEE, (2015)SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems., , , , , , , , , and 4 other author(s). IEEE Trans. Computers, 68 (5): 765-783 (2019)Securing bitstream integrity, confidentiality and authenticity in reconfigurable mobile heterogeneous systems., , , , , and . AQTR, page 1-6. IEEE, (2018)A Bayesian model for system level reliability estimation., , , , , , , and . ETS, page 1-2. IEEE, (2015)Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview., , , , , , , , , and 1 other author(s). Microprocess. Microsystems, 39 (8): 1204-1214 (2015)