Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.

Y. Son, H. Cho, Y. Ro, J. Lee, and J. Ahn. IEEE Comput. Archit. Lett., 16 (1): 76-79 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Young Hoon Paik

Young-Hoon Ko

Young Hoon Kwun

Young-Hoon Lee

Christina Hoon

Other publications of authors with the same name

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.K. Ha, S. Lee, Y. Park, H. Kwon, T. Oh, Y. Sohn, S. Bae, K. Park, J. Lee, C. Lee and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)Scalable high-radix router microarchitecture using a network switch organization.J. Ahn, Y. Son, and J. Kim. ACM Trans. Archit. Code Optim., 10 (3): 17:1-17:25 (2013)SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures.Y. Ro, H. Cho, E. Lee, D. Jung, Y. Son, J. Ahn, and J. Lee. HPCA, page 517-528. IEEE Computer Society, (2017)CiDRA: A cache-inspired DRAM resilience architecture.Y. Son, S. Lee, S. O, S. Kwon, N. Kim, and J. Ahn. HPCA, page 502-513. IEEE Computer Society, (2015)Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems.H. Moghaddam, Y. Son, J. Ahn, and N. Kim. MICRO, page 50:1-50:13. IEEE Computer Society, (2016)Understanding power-performance relationship of energy-efficient modern DRAM devices.S. Lee, Y. Ro, Y. Son, H. Cho, N. Kim, and J. Ahn. IISWC, page 110-111. IEEE Computer Society, (2017)A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.Y. Bae, J. Park, S. Rhee, S. Ko, Y. Jeong, K. Noh, Y. Son, J. Youn, Y. Chu, H. Cho and 9 other author(s). ISSCC, page 44-46. IEEE, (2012)Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices.S. Lee, H. Cho, Y. Son, Y. Ro, N. Kim, and J. Ahn. IEEE Access, (2018)Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os.D. Chang, Y. Son, J. Ahn, H. Kim, M. Ahn, M. Schulte, and N. Kim. ICCAD, page 747-754. IEEE, (2013)CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults.S. O, S. Kwon, Y. Son, Y. Park, and J. Ahn. IEEE Comput. Archit. Lett., 14 (1): 17-20 (2015)

BibSonomy

Disambiguation of "Son, Young Hoon"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.

Please choose a person to relate this publication to

Young Hoon Paik

Young-Hoon Ko

Young Hoon Kwun

Young-Hoon Lee

Christina Hoon

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Son, Young Hoon"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.

Please choose a person to relate this publication to

Young Hoon Paik

Young-Hoon Ko

Young Hoon Kwun

Young-Hoon Lee

Christina Hoon

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.