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A hardware configurable self-organizing map for real-time color quantization.

, , , , and . ICECS, page 336-339. IEEE, (2016)

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VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher., , , , and . DELTA, page 386-389. IEEE Computer Society, (2008)Cluster-Based Hybrid Reconfigurable Architecture for Auto-adaptive SoC., , and . ICECS, page 979-982. IEEE, (2007)Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design., , , and . IPDPS, page 178. IEEE Computer Society, (2003)High performance scalable hardware SOM architecture for real-time vector quantization., , and . IPAS, page 256-261. IEEE, (2018)A Multi-Application, Scalable and Adaptable Hardware SOM Architecture., , , , and . IJCNN, page 1-8. IEEE, (2019)Parallel architecture dedicated to connected component analysis., , , and . ICPR, page 699-703. IEEE Computer Society, (1996)Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC., , and . DELTA, page 153-157. IEEE Computer Society, (2008)An approach: FPGA based dynamically reconfigurable architecture to enable several scheme controls for power converters., , and . CCE, page 1-6. IEEE, (2012)FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding., , , , and . SoCC, page 423-426. IEEE, (2009)Linear array processors with multiple access modes memory for real-time image processing., , , , and . Real Time Imaging, 9 (3): 205-213 (2003)