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Architectural Support for Optimizing Huge Page Selection Within the OS., , , , , and . MICRO, page 1213-1226. ACM, (2023)Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows., , , , and . CGO, page 186-198. ACM, (2023)Prediction Based DRAM Row-Buffer Management in the Many-Core Era., , , and . PACT, page 183-184. IEEE Computer Society, (2011)Handling the problems and opportunities posed by multiple on-chip memory controllers., , , , and . PACT, page 319-330. ACM, (2010)The Architectural Implications of Distributed Reinforcement Learning on CPU-GPU Systems., , , , , , and . CoRR, (2020)FinePack: Transparently Improving the Efficiency of Fine-Grained Transfers in Multi-GPU Systems., , , , and . HPCA, page 516-529. IEEE, (2023)Micro-pages: increasing DRAM efficiency with locality-aware data placement., , , , , and . ASPLOS, page 219-230. ACM, (2010)Improving Operating System and Hardware Interactions Through Co-Design.. University of Utah, USA, (2014)Beyond block I/O: Rethinking traditional storage primitives., , , , and . HPCA, page 301-311. IEEE Computer Society, (2011)Selective GPU caches to eliminate CPU-GPU HW cache coherence., , , , , and . HPCA, page 494-506. IEEE Computer Society, (2016)