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Post-processing of clock trees via wiresizing and buffering for robust design.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (6): 691-701 (1996)

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Session details: Keynote.. ISPD, ACM, (2019)Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching., and . DAC, page 502-506. ACM Press, (1999)Performance computation for precharacterized CMOS gates with RC loads., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (5): 544-553 (1996)Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect., and . VLSI Design, page 476-. IEEE Computer Society, (1999)A sequential quadratic programming approach to concurrent gate and wire sizing., , and . ICCAD, page 144-151. IEEE Computer Society / ACM, (1995)RC interconnect synthesis-a moment fitting approach., , , and . ICCAD, page 418-425. IEEE Computer Society / ACM, (1994)A Gate-Delay Model for high-Speed CMOS Circuits., , , and . DAC, page 576-580. ACM Press, (1994)A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 574-591 (2007)Comparative Analysis of Conventional and Statistical Design Techniques., , , , , and . DAC, page 238-243. IEEE, (2007)Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization., , and . DAC, page 690-695. ACM Press, (1995)