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A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.

, , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 262-263. IEEE, (2008)

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Relax: an architectural framework for software recovery of hardware faults., , and . ISCA, page 497-508. ACM, (2010)A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation., , and . ITC, page 635-644. IEEE Computer Society, (2010)A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 41 (1): 54-62 (2006)A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design., , , , , , , , , and 2 other author(s). CICC, page 29-32. IEEE, (2008)BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency., and . SYSTOR, page 94-104. ACM, (2023)A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 262-263. IEEE, (2008)Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications., , , , , and . Proc. VLDB Endow., 14 (8): 1311-1324 (2021)Sampling + DMR: practical and low-overhead permanent fault detection., , , , , and . ISCA, page 201-212. ACM, (2011)A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism., , and . DSN, page 487-496. IEEE Computer Society, (2010)