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Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling.

, , and . DAC, page 28:1-28:6. ACM, (2014)

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Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1636-1648 (2016)Design Challenges of Intrachiplet and Interchiplet Interconnection., , , , , , , , and . IEEE Des. Test, 39 (6): 99-109 (2022)Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs., , , and . DAC, page 180:1-180:7. ACM, (2013)Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design., , and . ICCAD, page 3:1-3:8. IEEE, (2020)A Framework of Total Performance Improvement and Transaction Cost-driven Business Process Outsourcing Strategy., and . PACIS, page 76. AISeL, (2004)Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation., , , and . ICCAD, page 1-8. IEEE, (2021)Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs., , , and . ICCAD, page 649-655. IEEE, (2015)Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization., , , and . VLSI-DAT, page 1-4. IEEE, (2021)Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design., , and . ACM Great Lakes Symposium on VLSI, page 135-140. ACM, (2021)Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (12): 1964-1976 (2015)