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Disambiguation of "Esseni, David"

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Strain engineering of single-layer MoS2.

, , , , and . ESSDERC, page 314-317. IEEE, (2015)

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Wahyudi David

Florian Bodo David

Joachim David

Jens-Ulrich Davids

Heinz David

 

Other publications of authors with the same name

Reducing the Spike Rate in Deep Spiking Neural Networks., , and . ICONS, page 8:1-8:8. ACM, (2022)Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation., and . ESSDERC, page 215-218. IEEE, (2021)Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (2): 232-245 (2010)Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation., and . CoRR, (2022)Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2488-2498 (2014)Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies., , , , , and . CoRR, (2021)Performance study of strained III-V materials for ultra-thin body transistor applications., , , , , , , , , and 4 other author(s). ESSDERC, page 184-187. IEEE, (2016)The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs., , , , and . ESSCIRC, page 48-57. IEEE, (2007)Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (12): 2499-2512 (2014)Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (8): 1467-1472 (2012)