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Disambiguation of "Mizuno, Hiroyuki"

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A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing.

, , , , , and . IEEE J. Solid State Circuits, 51 (1): 303-309 (2016)

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Hiroyuki Tan

Hiroyuki Kobayashi

Jun Mizuno

Hiroyuki Okamuro

Hiroyuki Takada

 

Other publications of authors with the same name

Hierarchical power distribution and power management scheme for a single chip mobile processor., , , , , , , , , and 23 other author(s). DAC, page 292-295. ACM, (2006)24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing., , , , , and . ISSCC, page 1-3. IEEE, (2015)Mixbiotic society measures: Assessment of community well-going as living system., , , , , and . CoRR, (2023)Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution., , , , , and . Int. J. Netw. Comput., 6 (2): 195-211 (2016)Sensorimotor Visual Perception on Embodied System Using Free Energy Principle., , , and . PKDD/ECML Workshops (1), volume 1524 of Communications in Computer and Information Science, page 865-877. Springer, (2021)Spatial computing architecture using randomness of memory cell stability under voltage control., , , and . ECCTD, page 1-4. IEEE, (2013)Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers., , and . candar, page 196-202. IEEE, (2023)A 45nm 37.3GOPS/W heterogeneous multi-core SoC., , , , , , , , , and 9 other author(s). ISSCC, page 100-101. IEEE, (2010)Response Style Characterization for Repeated Measures Using the Visual Analogue Scale., , , , , and . CoRR, (2024)Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 42 (1): 74-83 (2007)