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Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.

, , , and . CCECE, page 538-543. IEEE, (2011)

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A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation.. ISCAS (5), page 213-216. IEEE, (2003)Rapid design space exploration for multi parametric optimization of VLSI designs., , and . ISCAS, page 3164-3167. IEEE, (2010)Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design., , and . Microprocess. Microsystems, 36 (4): 303-314 (2012)FPGA-Based adaptive digital predistortion for radio-over-fiber links., and . Microprocess. Microsystems, 30 (3): 145-154 (2006)An adaptive security framework with extensible computational complexity for cipher systems., , and . ICITST, page 133-140. IEEE, (2016)A New Adaptive Security Architecture with Extensible Computation Complexity for Generic Ciphers., and . J. Hardw. Syst. Secur., 3 (4): 319-337 (2019)Integrated design space exploration based on power-performance trade-off using genetic algorithm., , and . ACAI, page 77-81. ACM, (2011)A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies., and . CSICC, volume 6 of Communications in Computer and Information Science, page 653-660. (2008)Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget., and . CCECE, page 69-74. IEEE, (2015)Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis., , , and . CCECE, page 538-543. IEEE, (2011)