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Disambiguation of "Mitani, Hidenori"

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7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C.

, , , , , , , , , , , , and . ISSCC, page 140-141. IEEE, (2016)

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Hidenori Sakuma

 

Other publications of authors with the same name

SONOS 1Tr eFlash Memory., and . Embedded Flash Memory for Embedded Systems, Springer, (2018)A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier., , , , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 3094-3102 (2022)A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier., , , , , , , , , and 5 other author(s). A-SSCC, page 1-3. IEEE, (2021)7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C., , , , , , , , , and 3 other author(s). ISSCC, page 140-141. IEEE, (2016)A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 134-135. IEEE, (2022)A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications., , , , , , , , , and 2 other author(s). VLSI Circuits, page 202-. IEEE, (2019)15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs., , , , , , , , , and 1 other author(s). ISSCC, page 290-292. IEEE, (2024)A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (4): 1283-1292 (April 2024)