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A Model-Based Approach for Executable Specifications on Reconfigurable Hardware.

, , and . DATE, page 692-697. IEEE Computer Society, (2005)

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SPES Methodology and MARTE Constraints in Architectural Design., , , , and . ISCC, page 377-383. IEEE, (2018)Integration of Low Power Analysis into High-Level Scheduling in Distributed Real-Time Computing Systems., , and . DIPES, volume 219 of IFIP Conference Proceedings, page 205-215. Kluwer, (2002)Towards a Modular Communication System for FPGAs., , , , and . DELTA, page 71-76. IEEE Computer Society, (2004)Integration of Energy Reduction into High-Level Synthesis by Partitioning., and . DIPES, volume 225 of IFIP, page 225-234. Springer, (2006)Ein Modellierungsansatz für eine Systemarchitekturbeschreibung von Automotive-Systemen mit MARTE und SysML., , , and . Automatisierungstechnik, 67 (6): 490-501 (2019)Non-functional Constraints Annotation to Real-Time Embedded System Design., , , , and . SBESC, page 219-224. IEEE, (2018)Logistic Regression and Naive Bayes for Hierarchical Multi-label Classification at GermEval 2019 - Task 1., and . KONVENS, (2019)A model-based design space exploration for embedded image processing in industrial applications., , , , and . INDIN, page 434-439. IEEE, (2014)A new Design Partitioning Approach for Low Power High-Level Synthesis., and . DELTA, page 143-148. IEEE Computer Society, (2006)Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique., , and . IESS, volume 523 of IFIP Advances in Information and Communication Technology, page 88-99. Springer, (2015)