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Synthesis of threshold logic gates to nanoelectronics., , , and . SBCCI, page 1-6. IEEE, (2013)Design-oriented delay model for CMOS inverter., , and . SBCCI, page 1-6. IEEE, (2012)Binary adder circuit design using emerging MIGFET devices., , , , , and . ISQED, page 125-130. IEEE, (2017)CMOS inverter delay model based on DC transfer curve for slow input., , and . ISQED, page 651-657. IEEE, (2013)Constructive AIG optimization through functional composition., , and . ARCS Workshops, VDE-Verlag, (2011)CMOS logic gate performance variability related to transistor network arrangements., , and . Microelectron. Reliab., 49 (9-11): 977-981 (2009)Contributions to Modeling Patent Claims When Representing Patent Knowledge., , , and . AICOL, volume 10791 of Lecture Notes in Computer Science, page 140-156. Springer, (2017)Comparing Transistor-Level Implementations of 4-Input Logic Functions., , , and . IWLS, page 361-365. (2002)Optimization on cell-library design for digital Application Specific Printed Electronics Circuits., , , , and . PATMOS, page 1-6. IEEE, (2014)Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits., , , and . J. Low Power Electron., 6 (1): 192-200 (2010)