( en | de | ru )

 

Disambiguation of "Herdrich, Andrew"

Author of the publication

copydeleteadd this publication to your clipboard
Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family.

, , , , , , and . HPCA, page 657-668. IEEE Computer Society, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Georg Herdrich

Silke Herdrich

Jürgen Herdrich

Klaus Herdrich

Georg Herdrich

 

Other publications of authors with the same name

PIRATE: QoS and performance management in CMP architectures., , , , and . SIGMETRICS Perform. Evaluation Rev., 37 (4): 3-10 (2010)QoS management on heterogeneous architecture for parallel applications., , , , , and . ICCD, page 332-339. IEEE Computer Society, (2014)Advances in Microprocessor Cache Architectures Over the Last 25 Years., , , , , , , , and . IEEE Micro, 41 (6): 78-88 (2021)QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications., , , , , and . IEEE Syst. J., 11 (4): 2096-2107 (2017)CAF: Core to Core Communication Acceleration Framework., , , , and . PACT, page 351-362. ACM, (2016)Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System., , , , , , , and . Euro-Par, volume 7484 of Lecture Notes in Computer Science, page 232-245. Springer, (2012)RAPID: Enabling Fast Online Policy Learning in Dynamic Public Cloud Environments., , , , , , , , and . CoRR, (2023)RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization., , , , , , , , , and 1 other author(s). NetSoft, page 335-343. IEEE, (2020)Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family., , , , , , and . HPCA, page 657-668. IEEE Computer Society, (2016)Rate-based QoS techniques for cache/memory in CMP platforms., , , , , and . ICS, page 479-488. ACM, (2009)