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Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow.

, and . ACM Trans. Reconfigurable Technol. Syst., 10 (2): 11:1-11:23 (2017)

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Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy., , and . DATE, page 1550-1555. IEEE, (2016)From software threads to parallel hardware in high-level synthesis for FPGAs., , and . FPT, page 270-277. IEEE, (2013)Bitwidth-optimized hardware accelerators with software fallback., and . FPT, page 136-143. IEEE, (2013)Modulo SDC scheduling with recurrence minimization in high-level synthesis., , and . FPL, page 1-8. IEEE, (2014)High-Level Synthesis of FPGA Circuits with Multiple Clock Domains., and . FCCM, page 109-116. IEEE Computer Society, (2018)Clock power reduction for virtex-5 FPGAs., , and . FPGA, page 13-22. ACM, (2009)The VTR project: architecture and CAD for FPGAs from verilog to routing., , , , , , , , and . FPGA, page 77-86. ACM, (2012)Impact of FPGA architecture on resource sharing in high-level synthesis., , , , , , and . FPGA, page 111-114. ACM, (2012)High-level synthesis with LegUp: a crash course for users and researchers., , , and . FPGA, page 7-8. ACM, (2013)EASY: Efficient Arbiter SYnthesis from Multi-threaded Code., , , , and . FPGA, page 142-151. ACM, (2019)