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A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications.

, , , , , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 50 (1): 158-169 (2015)

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13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications., , , , , , , , , and 8 other author(s). ISSCC, page 232-233. IEEE, (2014)Pseudo NMOS based sense amplifier for high speed single-ended SRAM., , , , and . ICECS, page 331-334. IEEE, (2014)Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1059-1063 (2016)A 130-nm 0.9-V 66-MHz 8-Mb (256K × 32) local SONOS embedded flash EEPROM., , , , , , , and . IEEE J. Solid State Circuits, 40 (4): 877-883 (2005)Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1555-1563 (2015)Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1062-1070 (2015)Design of poly-Si TFT-LCD panel with integrated driver circuits for an HDTV/XGA projection system., , , , and . IEEE Trans. Consumer Electronics, 46 (1): 95-104 (2000)Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield., , , , , , , , , and . ISCAS, page 2541-2544. IEEE, (2015)Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (7): 1370-1374 (2015)