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A novel architecture design for VLSI implementation of integer DCT in HEVC standard., and . Multim. Tools Appl., 79 (33-34): 23977-23993 (2020)A new fast motion estimation algorithm using fast mode decision for high-efficiency video coding standard., , , , and . J. Real-Time Image Processing, 11 (4): 675-691 (2016)A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment., , , and . Int. J. Circuit Theory Appl., 49 (8): 2329-2347 (2021)A Hardware-Efficient Parallel Architecture for HEVC Deblocking Filter., , , and . SSD, page 669-673. IEEE, (2019)FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder., , , , and . Circuits and Systems, 1 (1): 18-29 (2010)A Novel Deblocking Filter Architecture for H.264/AVC., , , , and . J. Signal Process. Syst., 89 (2): 281-292 (2017)HEVC Decoder Analysis on ARM Processor., , , , and . SSD, page 842-845. IEEE, (2018)An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform., , , and . IPAS, page 1-6. IEEE, (2016)HW/SW TQ/IQT design for H.264/AVC., , and . ICECS, page 13-16. IEEE, (2011)Intelligent Measuring of the Volume Fraction Considering Temperature Changes and Independent Pressure Variations for a Two-Phase Homogeneous Fluid Using an 8-Electrode Sensor and an ANN., , , , , , , and . Sensors, 23 (15): 6959 (August 2023)