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An energy-efficient ternary interconnection link for asynchronous systems., , , and . ISCAS, IEEE, (2006)Self-Adaptive Networked Entities for Building Pervasive Computing Architectures., , , , and . ICES, volume 5216 of Lecture Notes in Computer Science, page 94-105. Springer, (2008)A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors., , and . DSD, page 756-763. IEEE, (2023)Exploration and design of embedded systems including neural algorithms., , , and . DATE, page 986-991. ACM, (2015)Parallel Architecture Benchmarking: From Embedded Computing to HPC, a FiPS Project Perspective., , , , and . EUC, page 154-161. IEEE Computer Society, (2014)Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions., , , and . J. Signal Process. Syst., 94 (10): 945-960 (2022)Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects., , and . ISQED, page 334-339. IEEE Computer Society, (2006)Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect., , and . Microelectron. J., 41 (8): 480-486 (2010)SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration., , , , , , , , , and 10 other author(s). CoRR, (2023)Analysis of on-chip communication properties in accelerator architectures for deep neural networks., and . NOCS, page 9-14. ACM, (2021)