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Disambiguation of "Kawaguchi, Hiroshi"

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A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm.

, , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2592-2599 (2015)

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Hirokazu Kawaguchi

Hiroshi Murata

Hiroshi Kawabe

Hiroshi Kubota

Hiroshi Uchida

 

Other publications of authors with the same name

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current., , and . IEEE J. Solid State Circuits, 35 (10): 1498-1501 (2000)A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture., , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3623-3633 (2006)A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2226-2233 (2012)A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (11): 2287-2294 (2011)Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's., , , , , , , , , and . IEICE Trans. Electron., 88-C (4): 760-767 (2005)A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond., , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3634-3641 (2006)A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2701-2708 (2011)An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 434-442 (2013)An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter., , , , and . IEICE Trans. Electron., 98-C (6): 489-495 (2015)Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (6): 1198-1205 (2016)