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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor., , , , , , , , , and 5 other author(s). ISSCC, page 98-99. IEEE, (2014)The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)Design and implementation of the POWER5 microprocessor., , , , , , , , , and 11 other author(s). DAC, page 670-672. ACM, (2004)26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection., , , , , , , , , and . ISSCC, page 444-445. IEEE, (2017)Reliability of Centralized vs. Parallel Software Models for Composable Storage Systems., and . QRS, page 534-542. IEEE, (2021)AIOps Essential to Unified Resiliency Management in Data Lakehouses., , , and . IEEE Big Data, page 4777-4781. IEEE, (2022)Optical Diagnostics for IBM POWER6- Microprocessor., , , , , , , , , and . ITC, page 1-9. IEEE Computer Society, (2008)