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Power/performance optimization of many-core processor SoCs., , , , , and . ISSCC, page 508-509. IEEE, (2012)The opportunity cost of low power design: a case study in circuit tuning., , , , and . ISLPED, page 133-138. ACM, (2009)The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)Design methodology for the IBM POWER7 microprocessor., , , , , , , , , and 15 other author(s). IBM J. Res. Dev., 55 (3): 9 (2011)POWER7TM local clocking and clocked storage elements., , , , , , , and . ISSCC, page 178-179. IEEE, (2010)On-chip timing uncertainty measurements on IBM microprocessors., , , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2007)Design and implementation of the POWER5 microprocessor., , , , , , , , , and 11 other author(s). DAC, page 670-672. ACM, (2004)Session 3 overview: Processors: High performance digital subcommittee., and . ISSCC, page 54-55. IEEE, (2012)26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection., , , , , , , , , and . ISSCC, page 444-445. IEEE, (2017)IBM POWER7+ design for higher frequency at fixed power., , , , , , , , and . IBM J. Res. Dev., (2013)