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HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms.

, , , , and . J. Signal Process. Syst., 85 (3): 341-353 (2016)

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TUTGNSS University based hardware/software GNSS receiver for research purposes., , , , and . UPINLBS, page 1-6. IEEE, (2010)System-Level Design for Partially Reconfigurable Hardware., , , and . ISCAS, page 2738-2741. IEEE, (2007)A Processor Core for 32 kbit/s G.726 ADPCM Codecs., and . ISCAS, page 1932-1935. IEEE, (1995)Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip., and . DDECS, page 186-191. IEEE Computer Society, (2006)Applying CDMA Technique to Network-on-Chip., , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (10): 1091-1100 (2007)Approximate computing for complexity reduction in timing synchronization., , and . EURASIP J. Adv. Signal Process., (2014)Multicore Software-Defined Radio Architecture for GNSS Receiver Signal Processing., , , and . EURASIP J. Embed. Syst., (2009)DSPxPlore: design space exploration methodology for an embedded DSP core., , , , and . SAC, page 876-883. ACM, (2004)Topology optimization for application-specific networks-on-chip., , , and . SLIP, page 53-60. ACM, (2004)Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation., and . IET Comput. Digit. Tech., 1 (5): 640-652 (2007)