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Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera.

, , , , , and . J. Real Time Image Process., 12 (4): 791-812 (2016)

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A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures., , , and . SCOPES, page 5-12. ACM, (2019)Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices., , , , and . Neural Comput. Appl., 19 (2): 283-297 (2010)A Methodology to Implement Real-Time Applications on Reconfigurable Circuits., , , and . Engineering of Reconfigurable Systems and Algorithms, page 188-200. CSREA Press, (2003)FPGA-based architecture for hardware compression/decompression of wide format images., , and . J. Real Time Image Process., 1 (2): 163-170 (2006)An hypervisor approach for mixed critical real-time UAV applications., , , and . PerCom Workshops, page 985-991. IEEE, (2019)Real-time H.264/AVC baseline decoder implementation on TMS320C6416., , , , and . J. Real-Time Image Processing, 7 (4): 215-232 (2012)Automatic Hardware/Software interface generation for SynDEx-mixte., , , and . ATSIP, page 512-516. IEEE, (2014)From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations., , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 934-943. Springer, (2003)AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1119-1123. Springer, (2004)From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations., and . MEMOCODE, page 123-. IEEE Computer Society, (2003)