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The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.

D. Pham, E. Behnen, M. Bolliger, H. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, B. Le, Y. Masubuchi, S. Posluszny, M. Riley, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, and K. Yazawa. CICC, page 45-49. IEEE, (2005)

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Horst-Dieter Wendel

Dieter F Hülser

Dieter F Kickingereder

Dieter F Kutz

Reinhard Wendel

Other publications of authors with the same name

A 32nm 0.5V-supply dual-read 6T SRAM.J. Kuang, J. Schaub, F. Gebara, D. Wendel, S. Saroop, T. Nguyen, T. Fröhnel, A. Müller, C. Durham, R. Sautter and 5 other author(s). CICC, page 1-4. IEEE, (2010)IBM POWER8 circuit design and energy optimization.V. Zyuban, J. Friedrich, D. Dreps, J. Pille, D. Plass, P. Restle, Z. Deniz, M. Ziegler, S. Chu, M. Islam and 13 other author(s). IBM J. Res. Dev., (2015)Custom circuit design as a driver of microprocessor performance.D. Allen, S. Dhong, H. Hofstee, J. Leenstra, K. Nowka, D. Stasiak, and D. Wendel. IBM J. Res. Dev., 44 (6): 799-822 (2000)The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.J. Kuang, J. Schaub, F. Gebara, D. Wendel, T. Fröhnel, S. Saroop, S. Nassif, and K. Nowka. IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2010-2016 (2011)POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.D. Wendel, R. Kalla, J. Warnock, R. Cargnoni, S. Chu, J. Clabes, D. Dreps, D. Hrusecky, J. Friedrich, M. Islam and 14 other author(s). IEEE J. Solid State Circuits, 46 (1): 145-161 (2011)Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, F. Kono, D. Nelson, O. Takahashi, S. Tokito, O. Torreiter and 2 other author(s). ISSCC, page 322-606. IEEE, (2007)The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor.D. Wendel, R. Kalla, R. Cargnoni, J. Clabes, J. Friedrich, R. Frech, J. Kahle, B. Sinharoy, W. Starke, S. Taylor and 4 other author(s). ISSCC, page 102-103. IEEE, (2010)Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.D. Pham, H. Anderson, E. Behnen, M. Bolliger, S. Gupta, H. Hofstee, P. Harvey, C. Johns, J. Kahle, A. Kameyama and 13 other author(s). ASP-DAC, page 871-878. IEEE, (2006)The POWER8TM processor: Designed for big data, analytics, and cloud environments.J. Friedrich, H. Le, W. Starke, J. Stuecheli, B. Sinharoy, E. Fluhr, D. Dreps, V. Zyuban, G. Still, C. Gonzalez and 10 other author(s). ICICDT, page 1-4. IEEE, (2014)The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.D. Pham, E. Behnen, M. Bolliger, H. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, B. Le, Y. Masubuchi and 8 other author(s). CICC, page 45-49. IEEE, (2005)

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Disambiguation of "Wendel, Dieter F."

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The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.

Please choose a person to relate this publication to

Horst-Dieter Wendel

Dieter F Hülser

Dieter F Kickingereder

Dieter F Kutz

Reinhard Wendel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wendel, Dieter F."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.

Please choose a person to relate this publication to

Horst-Dieter Wendel

Dieter F Hülser

Dieter F Kickingereder

Dieter F Kutz

Reinhard Wendel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.