( en | de | ru )

 

Disambiguation of "de Sousa, José T."

Author of the publication

copydeleteadd this publication to your clipboard
Fault Modeling and Defect Level Projections in Digital ICs.

, , , and . EDAC-ETC-EUROASIC, page 436-442. IEEE Computer Society, (1994)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

José Mácio Cavalcante Sousa

José Aleixo Sousa Proença

Theresa de Sousa

José Luis Cárdenas T

José Guillermo De Aguinaga

 

Other publications of authors with the same name

Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction., , and . IET Comput. Digit. Tech., 2 (1): 30-39 (2008)An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications., , , , and . ISCAS, page 1226-1229. IEEE, (2015)Heuristic-Based Backtracking Relaxation for Propositional Satisfiability., , , and . J. Autom. Reason., 35 (1-3): 3-24 (2005)Moving Deep Learning to the Edge., , , and . Algorithms, 13 (5): 125 (2020)Defect level evaluation in an IC design environment., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (10): 1286-1293 (1996)Improved diagnosis of realistic interconnect shorts., and . ED&TC, page 501-505. IEEE Computer Society, (1997)Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 344-353. Springer, (2004)IC Defects-Based Testability Analysis., , and . ITC, page 500-509. IEEE Computer Society, (1991)A fast SAT solver algorithm best suited to reconfigurable hardware., , and . SBCCI, page 131-136. ACM, (2006)A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware., , and . DAC, page 684-690. ACM Press, (1999)